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    Implementing Decay Techniques using 4T Quasi-Static Memory Cells
    13 years 11 months ago
    Implementing Decay Techniques using 4T Quasi-Static Memory Cells
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    Abstract-This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While ...
    Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin...
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