Implementing Decay Techniques using 4T Quasi-Static Memory Cells

Abstract-This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While 4T designs lose state when infrequently accessed, they have very low leakage, smaller area, and no capacitive loads to switch. This short paper gives an overview of 4T implementation issues and a preliminary evaluation of leakage-energy savings that shows improvements of 60-80%.

• Type: Journal
• Year: 2002
• Where: CAL
• Authors: Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Zhigang Hu, Margaret Martonosi, Douglas W. Clark
• Keywords: Branch Predictor Array, CAL 2002, CAL 2008, Leakage Power Dissipation, Low Leakage