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ICCAD
2003
IEEE
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ICCAD 2003
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Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
14 years 9 months ago
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www.eecs.umich.edu
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge
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