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ICCAD
1993
IEEE
121views Hardware» more  ICCAD 1993»
14 years 3 months ago
Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures
For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchic...
Arjan J. van Genderen, N. P. van der Meijs
ICCAD
1996
IEEE
164views Hardware» more  ICCAD 1996»
14 years 3 months ago
A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects
In this paper, we present a new capacitance extraction method named Dimension Reduction Technique (DRT) for 3D VLSI interconnects. The DRT converts a complex 3D problem into a ser...
Wei Hong II, Weikai Sun, Zhenhai Zhu, Hao Ji, Ben ...
GLVLSI
2008
IEEE
129views VLSI» more  GLVLSI 2008»
14 years 5 months ago
Variational capacitance modeling using orthogonal polynomial method
In this paper, we propose a novel statistical capacitance extraction method for interconnects considering process variations. The new method, called statCap, is based on the spect...
Jian Cui, Gengsheng Chen, Ruijing Shen, Sheldon X....