ICCAD 1996 - PDF Preprint Papers

ICCAD 1996 International Conference on Computer-Aided Design

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ICCAD
1996
IEEE

164views Hardware» more ICCAD 1996»

A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects

14 years 4 months ago

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In this paper, we present a new capacitance extraction method named Dimension Reduction Technique (DRT) for 3D VLSI interconnects. The DRT converts a complex 3D problem into a ser...

Wei Hong II, Weikai Sun, Zhenhai Zhu, Hao Ji, Ben ...

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Id	Views	Title	Status

1	164	A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects	claim
2	151	Expected current distributions for CMOS circuits	claim
3	144	Validation coverage analysis for complex digital designs	claim
4	141	An observability-based code coverage metric for functional simulation	claim
5	140	Register-transfer level estimation techniques for switching activity and power consumption	claim
6	133	Basic concepts for an HDL reverse engineering tool-set	claim
7	131	Multi-level logic optimization for low power using local logic transformations	claim
8	129	Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits	claim
9	127	Comparing models of computation	claim
10	123	Efficient solution of systems of Boolean equations	claim
11	122	Analytical delay models for VLSI interconnects under ramp input	claim
12	121	Identification of unsettable flip-flops for partial scan and faster ATPG	claim
13	119	An algorithm for synthesis of system-level interface circuits	claim
14	114	An efficient approach to simultaneous transistor and interconnect sizing	claim
15	112	GRASP - a new search algorithm for satisfiability	claim
16	111	Multi-level spectral hypergraph partitioning with arbitrary vertex sizes	claim
17	106	A general dispersive multiconductor transmission line model for interconnect simulation in SPICE	claim
18	106	Heterogeneous built-in resiliency of application specific programmable processors	claim
19	106	Buffered Steiner tree construction with wire sizing for interconnect layout optimization	claim
20	106	Interchangeable pin routing with application to package layout	claim
21	103	Metrics, techniques and recent developments in mixed-signal testing	claim
22	102	Bit-flipping BIST	claim
23	95	Semi-analytical techniques for substrate characterization in the design of mixed-signal ICs	claim
24	94	Metamorphosis: state assignment by retiming and re-encoding	claim
25	94	Metrology for analog module testing using analog testability bus	claim
26	93	ACV: an arithmetic circuit verifier	claim
27	93	VERILAT: verification using logic augmentation and transformations	claim
28	92	Generation of BDDs from hardware algorithm descriptions	claim
29	90	A coloring approach to the structural diagnosis of interconnects	claim
30	89	An algorithm for power estimation in switched-capacitor circuits	claim
31	88	Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling	claim
32	87	Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions	claim
33	86	Polarized observability don't cares	claim
34	86	Tearing based automatic abstraction for CTL model checking	claim
35	85	Exploiting regularity for low-power design	claim
36	81	Logic optimization by output phase assignment in dynamic logic synthesis	claim
37	80	Generalized constraint generation in the presence of non-deterministic parasitics	claim
38	78	Stratified random sampling for power estimation	claim
39	78	Design for manufacturability in submicron domain	claim
40	77	Power optimization in disk-based real-time application specific systems	claim
41	76	Directional bias and non-uniformity in FPGA global routing architectures	claim
42	74	Optimal non-uniform wire-sizing under the Elmore delay model	claim
43	73	Using complete-1-distinguishability for FSM equivalence checking	claim

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