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DATE
2006
IEEE
120views Hardware» more  DATE 2006»
14 years 5 months ago
Soft delay error analysis in logic circuits
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
Balkaran S. Gill, Christos A. Papachristou, Franci...