clock domains | Sciweavers

DAC
2005
ACM

114views Computer Architecture» more DAC 2005»

Multi-frequency wrapper design and optimization for embedded cores under average power constraints

14 years 2 months ago

This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...

Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty

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FPGA
2006
ACM

111views FPGA» more FPGA 2006»

FPGA clock network architecture: flexibility vs. area and power

14 years 4 months ago

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This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...

Julien Lamoureux, Steven J. E. Wilton

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