Multi-frequency wrapper design and optimization for embedded cores under average power constraints

This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed method improves upon a recent wrapper design method that requires a common shift frequency for the scan elements in the different clock domains. We present an integer linear programming (ILP) model that can be used to minimize the testing time for small problem instances. We also present an efficient heuristic method that is applicable to large problem instances, and which yields the same (optimal) testing time as ILP for small problem instances. Compared to recent work on wrapper design using a single shift frequency, we obtain lower testing times and the reduction in testing time is especially significant under power constraints. Categories and Subject Descriptors B.7.2 B.7.3 [Integrated Circuits]: [Design Aids, Reliability and Testing] General Terms Algorithms, Performance, Design, Reliability Keywords Wrapp...

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty
• Keywords: Clock Domains, Computer Architecture, DAC 2005, Multiple Clock Domains, Testing Time