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EURODAC
1995
IEEE
112views VHDL» more  EURODAC 1995»
14 years 4 months ago
Post routing performance optimization via tapered link insertion and wiresizing
Most existing performance-driven and clock routing algorithms can not guarantee performance after all nets are routed. This paper proposes a new post routing approach which can re...
Tianxiong Xue, Ernest S. Kuh