Post routing performance optimization via tapered link insertion and wiresizing

Most existing performance-driven and clock routing algorithms can not guarantee performance after all nets are routed. This paper proposes a new post routing approach which can reduce both maximum delay and skew of an existing routing topology by tapered link insertion and non-uniform wiresizing. It uses the Sequential Quadratic Programming method for constrained optimization. Experimental results show that our approach can improve performance signicantly and consume less area than uniform wiresizing.

• Type: Conference
• Year: 1995
• Where: EURODAC
• Authors: Tianxiong Xue, Ernest S. Kuh
• Keywords: Clock Routing Algorithms, EURODAC 1995, Post Routing Approach, Routing, VHDL