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33
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EURODAC
1994
IEEE
120
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VHDL
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EURODAC 1994
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Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
14 years 3 months ago
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vlsicad.ucsd.edu
Clock routing has become a critical issue in the layout design of high-performance systems. We show that the two passes bottom-up and top-down of the DME algorithm 2, 3, 4, 8 can ...
Chung-Wen Albert Tsao, Andrew B. Kahng
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