Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay

Clock routing has become a critical issue in the layout design of high-performance systems. We show that the two passes bottom-up and top-down of the DME algorithm 2, 3, 4, 8 can be replaced by a single topdown pass, which yields exactly the same optimal solution. From this, we develop a top-down algorithm which dynamically determines and embeds the clock tree topology, such that i the embedding is guaranteed to be planar, and ii the result has provably minimum total wirelength and minimum pathlength delay for that topology. A simple version of our method produces planar exact zero-skew solutions with total wirelengths that are competitive with the best non-planar exact zero-skew results in the literature.

• Type: Conference
• Year: 1994
• Where: EURODAC
• Authors: Chung-Wen Albert Tsao, Andrew B. Kahng
• Keywords: Clock Tree Topology, EURODAC 1994, Minimum Total Wirelength, Total Wirelengths, VHDL