ITC
1996
IEEE
13 years 11 months ago
1996
IEEE
A novel approach to testing CMOS digital circuits is presented that is based on an analysis of IDD switching transients on the supply rails and voltage transients at selected test...
ISQED
2006
IEEE
14 years 28 days ago
2006
IEEE
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...