APCCAS
2006
IEEE
14 years 3 months ago
2006
IEEE
A new low offset dynamic comparator for high resolution high speed analog-to-digital application has been designed. Inputs are reconfigured from the typical differential pair compa...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
— This paper presents the design of a combined two’s complement and IEEE 754-compliant floating-point comparator. Unlike previous designs, this comparator incorporates both op...
TAMC
2007
Springer
14 years 5 months ago
2007
Springer
In previous work we have introduced an average-case measure for the time complexity of Boolean circuits – that is the delay between feeding the input bits into a circuit and the ...