Sciweavers

DAC
2005
ACM
14 years 2 months ago
Smart diagnostics for configurable processor verification
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica’s latest configurable processor. Conventional ...
Sadik Ezer, Scott Johnson
DAC
2005
ACM
14 years 2 months ago
A combined feasibility and performance macromodel for analog circuits
The need to reuse the performance macromodels of an analog circuit topology challenges existing regression based modeling techniques. A model of good reusability should have a num...
Mengmeng Ding, Ranga Vemuri
DAC
2005
ACM
14 years 2 months ago
How accurately can we model timing in a placement engine?
This paper presents a novel placement algorithm for timing optimization based on a new and powerful concept, which we term differential timing analysis. Recognizing that accurate ...
Amit Chowdhary, Karthik Rajagopal, Satish Venkates...
DAC
2005
ACM
14 years 2 months ago
A pattern matching coprocessor for network security
Young H. Cho, William H. Mangione-Smith
DAC
2005
ACM
14 years 2 months ago
Closing the power gap between ASIC and custom: an ASIC perspective
We investigate differences in power between application-specific integrated circuits (ASICs) and custom integrated circuits, with examples from 0.6um to 0.13um CMOS. A variety of ...
David G. Chinnery, Kurt Keutzer
DAC
2005
ACM
14 years 2 months ago
Design methodology for wireless nodes with printed antennas
Jean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, M...
DAC
2005
ACM
14 years 2 months ago
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
Hongliang Chang, Vladimir Zolotov, Sambasivan Nara...
DAC
2005
ACM
14 years 2 months ago
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
Yu Cao, Lawrence T. Clark