Sciweavers

DAC
2005
ACM
14 years 2 months ago
Path delay test compaction with process variation tolerance
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths select...
Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, T...
DAC
2005
ACM
14 years 2 months ago
Prime clauses for fast enumeration of satisfying assignments to boolean circuits
Finding all satisfying assignments of a propositional formula has many applications in the design of hardware and software. An approach to this problem augments a clause-recording...
HoonSang Jin, Fabio Somenzi
DAC
2005
ACM
14 years 2 months ago
A variation tolerant subthreshold design approach
Nikhil Jayakumar, Sunil P. Khatri
DAC
2005
ACM
14 years 2 months ago
MIMO technology for advanced wireless local area networks
Jeffrey M. Gilbert, Won-Joon Choi, Qinfang Sun
DAC
2005
ACM
14 years 2 months ago
Performance space modeling for hierarchical synthesis of analog integrated circuits
Automated analog sizing is becoming an unavoidable solution for increasing analog design productivity. The complexity of typical analog SoC subsystems however calls for efficient ...
Georges G. E. Gielen, Trent McConaghy, Tom Eeckela...
DAC
2005
ACM
14 years 2 months ago
Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation
On-chip supply networks are playing an increasingly important role for modern nanometer-scale designs. However, the ever growing sizes of power grids make the analysis problem ext...
Peng Li
DAC
2005
ACM
14 years 2 months ago
An effective DFM strategy requires accurate process and IP pre-characterization
Carlo Guardiani, Massimo Bertoletti, Nicola Dragon...
DAC
2005
ACM
14 years 2 months ago
Exploring technology alternatives for nano-scale FPGA interconnects
Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular. With their regular structures, they are particularly amenable to scaling to smaller technologies. On the ...
Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane I...
DAC
2005
ACM
14 years 2 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes