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    ERSA
    2009
    129views Hardware» more  ERSA 2009»
    Data path Configuration Time Reduction for Run-time Reconfigurable Systems
    13 years 10 months ago
    Data path Configuration Time Reduction for Run-time Reconfigurable Systems
    Download  ce.et.tudelft.nl
    - The FPGA (re)configuration is a time-consuming process and a bottleneck in FPGA-based Run-Time Reconfigurable (RTR) systems. In this paper, we present a High Level Synthesis (HLS...
    Mahmood Fazlali, Ali Zakerolhosseini, Mojtaba Sabe...
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    IPPS
    2003
    IEEE
    130views Distributed And Parallel Com...» more  IPPS 2003»
    Performance and Overhead in a Hybrid Reconfigurable Computer
    14 years 5 months ago
    Performance and Overhead in a Hybrid Reconfigurable Computer
    Download  www.gwu.edu
    In this paper, we overview general hardware architecture and a programming model of SRC-6ETM reconfigurable computers, and compare the performance of the SRC-6E machine vs. IntelÂ...
    Osman Devrim Fidanci, Daniel S. Poznanovic, Kris G...
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