Data path Configuration Time Reduction for Run-time Reconfigurable Systems

- The FPGA (re)configuration is a time-consuming process and a bottleneck in FPGA-based Run-Time Reconfigurable (RTR) systems. In this paper, we present a High Level Synthesis (HLS) method, based on the data path merging technique to amortize the hardware configuration time in RTR systems. It merges the Data Flow Graphs (DFGs) of two or more computational intensive parts of the application and makes one general purpose data path (merged data path) which results in shorter bit-stream length and therefore reduces the configuration time. Our experimental results using the proposed method on mediabench applications, show up to 40% reduction in the configuration time compared to conventional synthesis method.

• Type: Journal
• Year: 2009
• Where: ERSA
• Authors: Mahmood Fazlali, Ali Zakerolhosseini, Mojtaba Sabeghi, Koen Bertels, Georgi Gaydadjiev
• Keywords: Configuration Time, Data Path, ERSA 2009, Hardware, Hardware Configuration Time