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36
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DAC
2009
ACM
174
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Computer Architecture
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DAC 2009
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A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
15 years 17 days ago
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www.ece.mtu.edu
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert
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