Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
: This paper develops a matching and scheduling algorithm that accounts for both the execution time and the power consumption of the application. The power consumption of different...
Saumya Uppaluri, Baback A. Izadi, Damu Radhakrishn...
We present an approach for Worst-Case Execution Time (WCET) Analysis of embedded system software, that is generated from Petri net specifications. The presented approach is part ...
The paper presents a technique for the design of digital circuits based on reusable hardware templates (HT). Any HT is being constructed in such a way that it might be employed for...
Future embedded systems (ES) will offer higher computation capacity than existing embedded systems. New applications of these ES require more and more memory resources and more an...
Most so-called “adiabatic” digital logic circuit families reported in the low-power design literature are actually not truly adiabatic, in that they do not satisfy the general...
− This paper presents an efficient system level power saving method for DRAM with multiple power modes. The proposed method is based on the power aware scheduling algorithm that ...
This paper presents a comparison of power-aware video decoding techniques that utilize Dynamic Voltage Scaling (DVS) capability. Three techniques were simulated and compared in te...
Eriko Nurvitadhi, Ben Lee, Chansu Yu, Myungchul Ki...
The combined benefits of Open Services Gateway Initiative (OSGi) and Smart card technologies in embedded devices have made the two technologies suitable for developing middleware ...
Patrick O. Bobbie, Sailaja H. Ramisetty, Abdul-Lat...