- This paper studies the routing problem for a new Field-Programmable Gate Array (FPGA) and Field-Programmable Interconnect Chip (FPIC) routing architecture which improves upon the...
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
An e cient solution to the wire sizing problem WSP usingthe Elmoredelaymodelisproposed. Two formulations of the problem are put forth: in the rst, the minimum interconnect delay i...
- This paper describes a symbolic formulation that allows incorporation of speculative operation execution (preexecution) in an exact control-dependent scheduling of arbitrary forw...
A new partitioningapproach for very largecircuits is described. We demonstrate that applying a recently developed analytical placement algorithm, that prots from a linear objecti...
Asynchronous circuits are crucial in designing low power and high performance digital systems. In this paper, we present an ecient modular partitioning approach for asynchronous c...
This paper introduces hot potato high level synthesis transformation techniques. These techniques add deflection operations in a computation in such a way that a specific goal is ...
Multi-dimensional(MD) systems are widely used in scientic applications such as image processing, geophysical signal processing and
uid dynamics. Earlier scheduling methods in syn...
Nelson L. Passos, Edwin Hsing-Mean Sha, Steven C. ...