Our goal is to transform a low-level circuit design into a more representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equiv...
We study the minimum-costbounded-skewrouting tree (BST) problem under the linear delay model. This problem captures several engineering tradeoffs in the design of routing topologi...
Dennis J.-H. Huang, Andrew B. Kahng, Chung-Wen Alb...
The Elmore delay is an extremely popular delay metric, particularly for RC tree analysis. The widespread usage of this metric is mainly attributable to it being the most accurate ...
Abstract—We present a new approach to event-driven simulation that does not use a centralized run-time event queue, yet is capable of handling arbitrary models, including those w...
Robert S. French, Monica S. Lam, Jeremy R. Levitt,...
—We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are cons...
Abstract A central problem in embedded system co-synthesis is the generation of software for lowlevel I O. Scheduling still remains a manual task because existing coarse-grained re...
— Software components for embedded reactive real-time applications must satisfy tight code size and runtime constraints. Cooperating finite state machines provide a convenient i...
Massimiliano Chiodo, Paolo Giusto, Attila Jurecska...