- We introduce a transformation, named rephasing, that manipulates the timing parameters in control-dataflow graphs. Traditionally high-level synthesis systems for DSP have either ...
We propose a novel optimization scheme that can improve the routing by reducing a newly observed router decaying effect. A pair of greedy-grow algorithms, each emphasizing a diffe...
Abstract We observe that the switching activity at a circuit node, also called the transition density, can be extremely sensitive to the circuit internal delays. As a result, sligh...
Abstract A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences t...
With the advent of portable and high-density microelectronic devices, the power dissipation of integrated circuits has become a critical concern. Accurate and e cient power estimat...
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
Noel Menezes, Satyamurthy Pullela, Lawrence T. Pil...
To save memory, layout-to-circuit extractors that use the Finite-Element Method for resistance extraction usually solve the corresponding set of equations with a frontal solution ...
A new approa ch for pe r f or ma nc e -dr ive n r outi ng i n hi ghly c onge st e d hi gh s pe e d MCMs a nd PCBs i s pr e s e nt e d. Gl oba l r out i ng i s e mpl oye d t o ma n...