Sciweavers

DAC
1995
ACM
13 years 11 months ago
Rephasing: A Transformation Technique for the Manipulation of Timing Constraints
- We introduce a transformation, named rephasing, that manipulates the timing parameters in control-dataflow graphs. Traditionally high-level synthesis systems for DSP have either ...
Miodrag Potkonjak, Mani B. Srivastava
DAC
1995
ACM
13 years 11 months ago
Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breue...
DAC
1995
ACM
13 years 11 months ago
Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing
We propose a novel optimization scheme that can improve the routing by reducing a newly observed router decaying effect. A pair of greedy-grow algorithms, each emphasizing a diffe...
Yu-Liang Wu, Malgorzata Marek-Sadowska
DAC
1995
ACM
13 years 11 months ago
Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits
Abstract We observe that the switching activity at a circuit node, also called the transition density, can be extremely sensitive to the circuit internal delays. As a result, sligh...
Farid N. Najm, Michael Y. Zhang
DAC
1995
ACM
13 years 11 months ago
Power Estimation in Sequential Circuits
Abstract A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences t...
Farid N. Najm, Shashank Goel, Ibrahim N. Hajj
DAC
1995
ACM
13 years 11 months ago
Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits
With the advent of portable and high-density microelectronic devices, the power dissipation of integrated circuits has become a critical concern. Accurate and e cient power estimat...
Farid N. Najm
DAC
1995
ACM
13 years 11 months ago
Symbolic Modeling and Evaluation of Data Paths
Chuck Monahan, Forrest Brewer
DAC
1995
ACM
13 years 11 months ago
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
Noel Menezes, Satyamurthy Pullela, Lawrence T. Pil...
DAC
1995
ACM
13 years 11 months ago
Delayed Frontal Solution for Finite-Element Based Resistance Extraction
To save memory, layout-to-circuit extractors that use the Finite-Element Method for resistance extraction usually solve the corresponding set of equations with a frontal solution ...
N. P. van der Meijs, Arjan J. van Genderen
DAC
1995
ACM
13 years 11 months ago
Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs
A new approa ch for pe r f or ma nc e -dr ive n r outi ng i n hi ghly c onge st e d hi gh s pe e d MCMs a nd PCBs i s pr e s e nt e d. Gl oba l r out i ng i s e mpl oye d t o ma n...
Sharad Mehrotra, Paul D. Franzon, Michael Steer