This paper presents a novel compiler for Esterel, a concurrent synchronous imperative language. It generates fast, small object code by compiling away concurrency, producing a sin...
eously demand shorter and less costly design cycles. Designing at higher levels of abstraction makes both objectives achievable, but enabling techniques like behavioral synthesis h...
The increasing complexity and software content of embedded systems has led to the common use of sophisticated system software that helps applications use the underlying hardware r...
Robert P. Dick, Ganesh Lakshminarayana, Anand Ragh...
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
In this paper, we study the incremental t echnology mapping problem for lookup-table (LUT) based Field Programmable Gate Arrays (FPGAs) under incremental changes. Given a gate-lev...
The use of deep submicron process technologies presents several new challenges in the area of manufacturing test. While a significant body of work has been devoted to identifying ...
Kwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik...
We investigate the differences in speed between applicationspecific integrated circuits and custom integrated circuits when each are implemented in the same process technology, wi...
A main advantage of control composition with modal processes [4] is the enhanced retargetability of the composed behavior over a wide variety of target architectures. Unlike previ...