CL
2000
Springer
14 years 4 months ago
2000
Springer
We use Kleene algebra with tests to verify a wide assortment of common compiler optimizations, including dead code elimination, common subexpression elimination, copy propagation,...
PEPM
2009
ACM
16 years 23 days ago
2009
ACM
The Verilog hardware description language has padding semantics that allow designers to write descriptions where wires of different bit widths can be interconnected. However, many ...