Static Consistency Checking for Verilog Wire Interconnects

The Verilog hardware description language has padding semantics that allow designers to write descriptions where wires of different bit widths can be interconnected. However, many of these connections are nothing more than bugs inadvertently introduced by the designer and often result in circuits that behave incorrectly or use more resources than required. A similar problem occurs when wires are incorrectly indexed by values (or ranges) that exceed their bounds. These two problems are exacerbated by generate blocks. While desirable for reusability and conciseness, the use of generate blocks to describe circuit families only makes the situation worse as it hides such inconsistencies making them harder to detect. Inconsistencies in the generated code are only exposed after elaboration when the code is fully-expanded. In this paper we show that these inconsistencies can be pinned down prior to elaboration using static analysis.We combine dependent types and constraint generation to red...

• Type: Conference
• Year: 2009
• Where: PEPM
• Authors: Cherif Salama, Gregory Malecha, Walid Taha, Jim Grundy, John O’Leary
• Keywords: Dead Code Elimination, Dependent Types, Static Array Bounds Checking, Verilog Elaboration, Verilog Wire Width Consistency