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27
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ICCAD
2006
IEEE
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Hardware
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ICCAD 2006
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Information theoretic approach to address delay and reliability in long on-chip interconnects
14 years 7 months ago
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www.cecs.uci.edu
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
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