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    CDES
    2009
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    Delay-Insensitive Ternary Logic
    14 years 20 days ago
    Delay-Insensitive Ternary Logic
    Download  comp.uark.edu
    This paper develops a delay-insensitive (DI) digital design paradigm that utilizes ternary logic as an alternative to dual-rail logic for encoding the DATA and NULL states. This ne...
    Ravi Sankar Parameswaran Nair, Scott C. Smith, Jia...
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