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ISVLSI
2007
IEEE
230views VLSI» more  ISVLSI 2007»
14 years 6 months ago
A Methodology and Toolset to Enable SystemC and VHDL Co-simulation
The new design challenges imposed by the increasing difficulties of today’s electronic systems obligated designers to develop new methodologies. System-level design and Platfor...
Richard Maciel, Bruno Albertini, Sandro Rigo, Guid...
IROS
2007
IEEE
124views Robotics» more  IROS 2007»
14 years 6 months ago
Design of an automated transportation system in a seaport container terminal for the reliability of operating robots
— For the design of an automated transportation system in an actual seaport container terminal, it is necessary to take into consideration the maintenance of operating robots (AG...
Satoshi Hoshino, Jun Ota
ICRA
2007
IEEE
122views Robotics» more  ICRA 2007»
14 years 6 months ago
Integrated Design Methodology for an Automated Transportation System in a Seaport Terminal
Abstract— Automation of transportation systems and promotion of the operations are becoming an international demand on seaport container terminals. For this issue, we propose an ...
Satoshi Hoshino, Jun Ota
ICDIM
2007
IEEE
14 years 6 months ago
An expert system for the design of agents
The growing interest for the design and development of multi-agent systems has brought to the creation of a specific research area called Agent-Oriented Software Engineering (AOS...
Massimo Cossentino, Luca Sabatucci, Valeria Seidit...
HPCS
2007
IEEE
14 years 6 months ago
Improved Grid Metascheduler Design using the Plackett-Burman Methodology
In the context of computational grids, a metascheduler is the service responsible for scheduling jobs across many geographically distributed processor clusters. Typically, these s...
Daniel C. Vanderster, Nikitas J. Dimopoulos, Randa...
GLVLSI
2007
IEEE
140views VLSI» more  GLVLSI 2007»
14 years 6 months ago
Structured and tuned array generation (STAG) for high-performance random logic
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kos...
GLVLSI
2007
IEEE
107views VLSI» more  GLVLSI 2007»
14 years 6 months ago
Side-channel resistant system-level design flow for public-key cryptography
In this paper, we propose a new design methodology to assess the risk for side-channel attacks, more specifically timing analysis and simple power analysis, at an early design st...
Kazuo Sakiyama, Elke De Mulder, Bart Preneel, Ingr...
DATE
2007
IEEE
143views Hardware» more  DATE 2007»
14 years 6 months ago
Portable multimedia SoC design: a global challenge
- The intrinsic capability brought by each new technology node opens the way to a broad range of system integration options and continuously enables new applications to be integrat...
Maurizio Paganini, Georg Kimmich, Stephane Ducrey,...
DATE
2007
IEEE
73views Hardware» more  DATE 2007»
14 years 6 months ago
Design methods for security and trust
The design of ubiquitous and embedded computers focuses on cost factors such as area, power-consumption, and performance. Security and trust properties, on the other hand, are oft...
Ingrid Verbauwhede, Patrick Schaumont
AHS
2007
IEEE
262views Hardware» more  AHS 2007»
14 years 6 months ago
Addressing the Metric Challenge: Evolved versus Traditional Fault Tolerant Circuits
The field of Evolvable Hardware, applying artificial evolution to the design of digital and analogue hardware is around ten years old. However, the field is far from reaching m...
Pauline C. Haddow, Morten Hartmann, Asbjørn...