Sciweavers

PARELEC
2006
IEEE
14 years 5 months ago
A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments
Modern microprocessors get more and more susceptible to transient faults, e.g. caused by high-energetic particles due to high integration, clock frequencies, temperature and decre...
Bernhard Fechner
PARELEC
2006
IEEE
14 years 5 months ago
Hierarchical Partitioning for Piecewise Linear Algorithms
processor arrays can be used as accelerators for a plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor arr...
Hritam Dutta, Frank Hannig, Jürgen Teich
PARELEC
2006
IEEE
14 years 5 months ago
Application-Driven Development of Concurrent Packet Processing Platforms
We have developed an application-driven methodology for implementing parallel and heterogeneous programmable platforms. We deploy our flow for network access platforms where we h...
Christian Sauer, Matthias Gries, Jörg-Christi...
IPPS
2006
IEEE
14 years 5 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell
IPPS
2006
IEEE
14 years 5 months ago
Compatible phase co-scheduling on a CMP of multi-threaded processors
The industry is rapidly moving towards the adoption of Chip Multi-Processors (CMPs) of Simultaneous MultiThreaded (SMT) cores for general purpose systems. The most prominent use o...
Ali El-Moursy, R. Garg, David H. Albonesi, Sandhya...
IPPS
2006
IEEE
14 years 5 months ago
A high level SoC power estimation based on IP modeling
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
David Elléouet, Nathalie Julien, Dominique ...