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36
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DAC
1996
ACM
115
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Computer Architecture
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DAC 1996
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Bit-Level Analysis of an SRT Divider Circuit
14 years 3 months ago
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www.cs.cmu.edu
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for t...
Randal E. Bryant
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