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    ISLPED
    2010
    ACM
    128views Hardware» more  ISLPED 2010»
    Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
    14 years 26 days ago
    Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
    Download  web.ics.purdue.edu
    DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
    Ahmed M. Amin, Zeshan Chishti
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    ISPASS
    2007
    IEEE
    80views Software Engineering» more  ISPASS 2007»
    DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving
    14 years 9 months ago
    DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving
    Download  www.ece.uic.edu
    We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core processors. FB-DIMM has a unique two-level interconnect structure, with FB-DIM...
    Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhan...
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