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DSD
2007
IEEE
83views Hardware» more  DSD 2007»
14 years 7 months ago
Hierarchical Identification of Untestable Faults in Sequential Circuits
Similar to sequential test pattern generation, the problem of identifying untestable faults in sequential circuits remains unsolved. Most of the previous works in untestability id...
Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kru...
DSD
2007
IEEE
150views Hardware» more  DSD 2007»
14 years 7 months ago
Adaptive Distance Estimation and Localization in WSN using RSSI Measures
Abstract—Localization is one of the most challenging and important issues in wireless sensor networks (WSNs), especially if cost-effective approaches are demanded. In this paper,...
Abdalkarim Awad, Thorsten Frunzke, Falko Dressler
DSD
2007
IEEE
96views Hardware» more  DSD 2007»
14 years 7 months ago
Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties
Jaroslav Skarvada, Tomas Herrman, Zdenek Kot&aacut...
DSD
2007
IEEE
120views Hardware» more  DSD 2007»
14 years 7 months ago
Latency Minimization for Synchronous Data Flow Graphs
Synchronous Data Flow Graphs (SDFGs) are a very useful means for modeling and analyzing streaming applications. Some performance indicators, such as throughput, have been studied b...
Amir Hossein Ghamarian, Sander Stuijk, Twan Basten...
DSD
2007
IEEE
87views Hardware» more  DSD 2007»
14 years 7 months ago
On the Construction of Small Fully Testable Circuits with Low Depth
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small ...
Görschwin Fey, Anna Bernasconi, Valentina Cir...
DSD
2007
IEEE
98views Hardware» more  DSD 2007»
14 years 7 months ago
Fault Diagnosis in Integrated Circuits with BIST
This paper presents an optimized fault diagnosing procedure applicable in Built-in Self-Test environments. Instead of the known approach based on a simple bisection of patterns in...
Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evart...
DSD
2007
IEEE
116views Hardware» more  DSD 2007»
14 years 7 months ago
Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation
This paper focuses on numerical function generators (NFGs) based on k-th order polynomial approximations. We show that increasing the polynomial order k reduces significantly the...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
DSD
2007
IEEE
86views Hardware» more  DSD 2007»
14 years 7 months ago
Toggle Equivalence Preserving (TEP) Logic Optimization
Eugene Goldberg, Kanupriya Gulati, Sunil P. Khatri
DSD
2007
IEEE
164views Hardware» more  DSD 2007»
14 years 7 months ago
An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation
In this paper, we present an efficient hardware architecture for real-time implementation of quarter-pixel accurate variable block size motion estimation for H.264 / MPEG4 Part 10...
Serkan Oktem, Ilker Hamzaoglu
DSD
2007
IEEE
114views Hardware» more  DSD 2007»
14 years 7 months ago
General Digit-Serial Normal Basis Multiplier with Distributed Overlap
We present the architecture of digit-serial normal basis multiplier over GF(2m ). The multiplier was derived from the multiplier of Agnew et al. Proposed multiplier is scalable by...
Martin Novotný, Jan Schmidt