Sciweavers

DSD
2009
IEEE
133views Hardware» more  DSD 2009»
14 years 6 months ago
Deductive Fault Simulation for Asynchronous Sequential Circuits
Roland Dobai, Elena Gramatová
DSD
2009
IEEE
95views Hardware» more  DSD 2009»
14 years 6 months ago
The Parallel Sieve Method for a Virus Scanning Engine
This paper shows a new architecture for a virus scanning system, which is different from that of an intrusion detection system. The proposed method uses two-stage matching: In the...
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura,...
DSD
2009
IEEE
90views Hardware» more  DSD 2009»
14 years 6 months ago
Instruction Precomputation for Fault Detection
—Fault tolerance (FT) is becoming increasingly important in computing systems. This work proposes and evaluates the instruction precomputation technique to detect hardware faults...
Demid Borodin, Ben H. H. Juurlink, Stefanos Kaxira...
DSD
2009
IEEE
387views Hardware» more  DSD 2009»
14 years 6 months ago
Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator
—This paper presents the design and implementation of a baseband demodulator for DVB-S2 satellite receivers. In order to meet the requirements of different complex and multidomai...
Panayiotis Savvopoulos, Nikolaos Papandreou, Theod...
DSD
2009
IEEE
84views Hardware» more  DSD 2009»
14 years 6 months ago
Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures
— 3D stacked architectures provide significant benefits in performance, footprint and yield. However, vertical stacking increases the thermal resistances, and exacerbates tempe...
Ayse Kivilcim Coskun, Andrew B. Kahng, Tajana Simu...
DSD
2009
IEEE
77views Hardware» more  DSD 2009»
14 years 6 months ago
Pulse Generation for On-chip Data Transmission
Abstract—Pulse-based data transmission has been demonstrated as a power-saving and high performance alternative to level-based signalling over global distances. Key to its correc...
Simon Hollis
DSD
2009
IEEE
124views Hardware» more  DSD 2009»
14 years 6 months ago
Network-on-Chip Architecture Exploration Framework
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...
Timo Schönwald, Jochen Zimmermann, Oliver Bri...
DSD
2009
IEEE
85views Hardware» more  DSD 2009»
14 years 6 months ago
Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment
—Long test application time and high temperature have become two major issues of system-on-chip (SoC) test. In order to minimize test application times and avoid overheating duri...
Zhiyuan He, Zebo Peng, Petru Eles
DSD
2009
IEEE
111views Hardware» more  DSD 2009»
14 years 6 months ago
Robustness Check for Multiple Faults Using Formal Techniques
Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft error...
Stefan Frehse, Görschwin Fey, André S&...