126
Voted
DSN
2007
IEEE
15 years 7 months ago
2007
IEEE
Continuous data protection, which logs every update to a file system, is an enabling technology to protect file systems against malicious attacks and/or user mistakes, because it ...
120
Voted
DSN
2007
IEEE
15 years 10 months ago
2007
IEEE
125
Voted
DSN
2007
IEEE
15 years 10 months ago
2007
IEEE
Programmable logic arrays (PLA), which can implement arbitrary logic functions in a two-level logic form, are promising as platforms for nanoelectronic logic due to their highly r...
114
Voted
DSN
2007
IEEE
15 years 10 months ago
2007
IEEE
A quorum system is a collection of sets (quorums) of servers, where any two quorums intersect. Quorumbased protocols underly modern edge-computing architectures and throughput-sca...
149
Voted
DSN
2007
IEEE
15 years 10 months ago
2007
IEEE
In this paper, we present a variational Bayesian (VB) approach to computing the interval estimates for nonhomogeneous Poisson process (NHPP) software reliability models. This appr...
107
Voted
DSN
2007
IEEE
15 years 10 months ago
2007
IEEE
Full duplication of an entire application (through spatial or temporal redundancy) would detect many errors that are benign to the application from the perspective of the end-user...
156
Voted
DSN
2007
IEEE
15 years 10 months ago
2007
IEEE
In this paper, we study replication techniques for scaling and continuous operation for a dynamic content server. Our focus is on supporting transparent and fast reconfiguration ...
99
Voted
DSN
2007
IEEE
15 years 10 months ago
2007
IEEE
In this paper, we study and model a crash-recovery target and its failure detector’s probabilistic behavior. We extend Quality of Service (QoS) metrics to measure the recovery d...
128
Voted
DSN
2007
IEEE
15 years 10 months ago
2007
IEEE
Autonomous robots offer alluring perspectives in numerous application domains: space rovers, satellites, medical assistants, tour guides, etc. However, a severe lack of trust in t...
126
Voted
DSN
2007
IEEE
15 years 10 months ago
2007
IEEE
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...