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    IDDQ Test: Will It Survive the DSM Challenge?
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    IDDQ Test: Will It Survive the DSM Challenge?
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    Sagar S. Sabade, D. M. H. Walker
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    Image Processing Techniques for Wafer Defect Cluster Identification
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    Image Processing Techniques for Wafer Defect Cluster Identification
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    Chenn-Jung Huang, Chua-Chin Wang, Chi-Feng Wu
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    Analyzing and Diagnosing Interconnect Faults in Bus-Structured Systems
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    Analyzing and Diagnosing Interconnect Faults in Bus-Structured Systems
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    Jun Zhao, Fred J. Meyer, Fabrizio Lombardi
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    Annual Index
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    Annual Index
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    nline search of authors and a broader subject search of abstracts of Young Children articles since 1985, volume 40, and of other articles published online since September 2002, vis...
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    The Cost of Design
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    The Cost of Design
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    Building a community
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    Building a community
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    Embedded Timing Analysis: A SoC Infrastructure
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    Embedded Timing Analysis: A SoC Infrastructure
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    Sassan Tabatabaei, André Ivanov
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    Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic
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    Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic
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    Greg Stitt, Frank Vahid
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    Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits
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    Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits
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    Michael H. Perrott
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    StepNP: A System-Level Exploration Platform for Network Processors
    13 years 10 months ago
    StepNP: A System-Level Exploration Platform for Network Processors
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    Pierre G. Paulin, Chuck Pilkington, Essaid Bensoud...
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