This paper presents a new adaptive scheme to reduce the computation energy of the discrete cosine transform (DCT) architecture for image/video coding. The scheme employs the noise ...
Abstract— This paper presents an exploration framework which performs data assignment and access scheduling exploration for applications given a multilayer memory architecture. O...
Radoslaw Szymanek, Francky Catthoor, Krzysztof Kuc...
This paper presents a structured application design trajectory to transform media-processing applications— modeled as Kahn process network—into a set of functionspecific hardw...
Martijn J. Rutten, Om Prakash Gangwal, Jos T. J. v...
— Workload design is a well recognized problem in the domain of microprocessor design. Different program characteristics that influence the selection of a representative workloa...
Alexander Maxiaguine, Samarjit Chakraborty, Wei Ts...
We proposed a hardware accelerator IP for the Tier-1 portion of Embedded Block Coding with Optimal Truncation (EBCOT) used in the JPEG2000 next generation image compression standa...
We present an evaluation strategy for clock synchronization algorithms. It is based on a combination of measured traces, which provide for realistic performance estimation, and of...
Abstract—Few analytical performance models that relate performance figure of merit to architectural design decisions are reported in recent studies of network-on-chip, which pre...