: We present a method for obtaining a minimal set of test configurations and their associated set oftest patterns that completely tests re-programmable Programmable Logic Arrays (P...
Charles E. Stroud, James R. Bailey, Johan R. Emmer...
An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum num...
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...