Deterministic BIST with Partial Scan

An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum number of flipflops to be scannable so that the remaining circuit has a pipeline-like structure. Experiments show that scanning less flipflops may even decrease the hardware overhead for the on-chip pattern generator besides the classical advantages of partial scan such as less impact on the system performance and less hardware overhead.

• Type: Journal
• Year: 2000
• Where: ET
• Authors: Gundolf Kiefer, Hans-Joachim Wunderlich
• Keywords: Efficient Deterministic Bist, ET 2000, Partial Scan, Partial Scan Chains