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ET
2008
92views more  ET 2008»
13 years 12 months ago
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware harde...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
ET
2006
72views more  ET 2006»
14 years 14 days ago
Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic System Assembly
In this paper, an optimization methodology is used to select the locations and characteristics of test, diagnosis and rework operations in electronic systems assembly processes. Re...
Zhen Shi, Peter Sandborn
ET
2006
98views more  ET 2006»
14 years 14 days ago
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults
1 Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of the...
Yu-Chiun Lin, Shi-Yu Huang
ET
2006
80views more  ET 2006»
14 years 14 days ago
Security Extension for IEEE Std 1149.1
A security extension for IEEE Std 1149.1 is proposed. It provides a locking mechanism which prevents unauthorised users to interfere via test bus with the system normal operation. ...
Franc Novak, Anton Biasizzo
ET
2006
55views more  ET 2006»
14 years 14 days ago
Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems
Recent years have seen the emergence of dropletbased microfluidic systems for safety-critical biomedical applications. In order to ensure reliability, microsystems incorporating m...
Fei Su, Sule Ozev, Krishnendu Chakrabarty
ET
2006
154views more  ET 2006»
14 years 14 days ago
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults
We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIS...
Jack Smith, Tian Xia, Charles E. Stroud
ET
2006
120views more  ET 2006»
14 years 14 days ago
Automatic Test Pattern Generation for Resistive Bridging Faults
An ATPG for resistive bridging faults is proposed that combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced s...
Piet Engelke, Ilia Polian, Michel Renovell, Bernd ...