Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware harde...
In this paper, an optimization methodology is used to select the locations and characteristics of test, diagnosis and rework operations in electronic systems assembly processes. Re...
1 Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of the...
A security extension for IEEE Std 1149.1 is proposed. It provides a locking mechanism which prevents unauthorised users to interfere via test bus with the system normal operation. ...
Recent years have seen the emergence of dropletbased microfluidic systems for safety-critical biomedical applications. In order to ensure reliability, microsystems incorporating m...
We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIS...
An ATPG for resistive bridging faults is proposed that combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introduced s...
Piet Engelke, Ilia Polian, Michel Renovell, Bernd ...