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ETS
2010
IEEE
153views Hardware» more  ETS 2010»
13 years 10 months ago
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes
ÑIn this paper, we present a comparative study on the effects of resistive-bridging defects in the SRAM core-cells, considering different technology nodes. In particular, we analy...
Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio,...
ETS
2010
IEEE
150views Hardware» more  ETS 2010»
13 years 10 months ago
Predicting dynamic specifications of ADCs with a low-quality digital input signal
— A new method is presented to test dynamic parameters of Analogue-to-Digital Converters (ADC). A noisy and nonlinear pulse is applied as the test stimulus, which is suitable for...
Xiaoqin Sheng, Vincent Kerzerho, Hans G. Kerkhoff
ETS
2010
IEEE
140views Hardware» more  ETS 2010»
14 years 17 days ago
Increasing reliability of programmable mixed-signal systems by applying design diversity redundancy
This paper explores the concept of design diversity redundancy applied to mixed-signal (MS) circuit blocks, as a proposal to increase system reliability. Three different implement...
Gabriel de M. Borges, Luiz F. Gonçalves, Ti...
ETS
2010
IEEE
150views Hardware» more  ETS 2010»
14 years 17 days ago
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs
It was shown in the past that ATPG based on the Boolean Satisfiability problem is a beneficial complement to traditional ATPG techniques. Its advantages can be observed especially ...
Daniel Tille, Stephan Eggersglüß, Rene ...
ETS
2010
IEEE
174views Hardware» more  ETS 2010»
14 years 17 days ago
Test-architecture optimization for TSV-based 3D stacked ICs
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakr...
ETS
2010
IEEE
130views Hardware» more  ETS 2010»
14 years 17 days ago
A distributed architecture to check global properties for post-silicon debug
Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking g...
Erik Larsson, Bart Vermeulen, Kees Goossens