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IPPS
1998
IEEE
14 years 3 months ago
A Mapping Methodology for Designing Software Task Pipelines for Embedded Signal Processing
Abstract. In this paper, we present a methodology for mapping an Embedded Signal Processing ESP application onto HPC platforms such that the throughput performance is maximized. Pr...
Myungho Lee, Wenheng Liu, Viktor K. Prasanna
HPCA
1998
IEEE
14 years 3 months ago
Performance Study of a Concurrent Multithreaded Processor
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chu...
IPPS
2000
IEEE
14 years 3 months ago
Combining Fusion Optimizations and Piecewise Execution of Nested Data-Parallel Programs
Abstract. Nested data-parallel programs often have large memory requirements due to their high degree of parallelism. Piecewise execution is an implementation technique used to min...
W. Pfannenstiel
IPPS
2000
IEEE
14 years 3 months ago
Controlling Distributed Shared Memory Consistency from High Level Programming Languages
One of the keys for the success of parallel processing is the availability of high-level programming languages for on-the-shelf parallel architectures. Using explicit message passi...
Yvon Jégou
LCPC
2009
Springer
14 years 4 months ago
MIMD Interpretation on a GPU
Programming heterogeneous parallel computer systems is notoriously difficult, but MIMD models have proven to be portable across multi-core processors, clusters, and massively paral...
Henry G. Dietz, B. Dalton Young
CAISE
2004
Springer
14 years 4 months ago
Enabling Personalized Composition and Adaptive Provisioning of Web Services
Abstract. The proliferation of interconnected computing devices is fostering the emergence of environments where Web services made available to mobile users are a commodity. Unfort...
Quan Z. Sheng, Boualem Benatallah, Zakaria Maamar,...
ASAP
2006
IEEE
145views Hardware» more  ASAP 2006»
14 years 5 months ago
2D-VLIW: An Architecture Based on the Geometry of Computation
This work proposes a new architecture and execution model called 2D-VLIW. This architecture adopts an execution model based on large pieces of computation running over a matrix of...
Ricardo Santos, Rodolfo Azevedo, Guido Araujo
IPPS
2008
IEEE
14 years 6 months ago
Model-based fault localization in large-scale computing systems
We propose a new fault localization technique for software bugs in large-scale computing systems. Our technique always collects per-process function call traces of a target system...
Naoya Maruyama, Satoshi Matsuoka
DATE
2009
IEEE
120views Hardware» more  DATE 2009»
14 years 6 months ago
Towards a formal semantics for the AADL behavior annex
—AADL is an Architecture Description Language which describes embedded real-time systems. Behavior annex is an extension of the dispatch mechanism of AADL execution model. This p...
Zhibin Yang, Kai Hu, Dianfu Ma, Lei Pi
ICS
2009
Tsinghua U.
14 years 6 months ago
Combining thread level speculation helper threads and runahead execution
With the current trend toward multicore architectures, improved execution performance can no longer be obtained via traditional single-thread instruction level parallelism (ILP), ...
Polychronis Xekalakis, Nikolas Ioannou, Marcelo Ci...