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    ICCAD
    2007
    IEEE
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    Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
    14 years 8 months ago
    Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
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    — Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
    Yu Hu, Satyaki Das, Steven Trimberger, Lei He
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