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DATE
2006
IEEE
140views Hardware» more  DATE 2006»
14 years 5 months ago
A hybrid framework for design and analysis of fault-tolerant architectures
It is anticipated that self assembled ultra-dense nanomemories will be more susceptible to manufacturing defects and transient faults than conventional CMOS-based memories, thus t...
Debayan Bhaduri, Sandeep K. Shukla, Deji Coker, Va...