In this paper we advocate the use of pre-decoding for CAM-based pattern matching. We implement an FPGA based sub-system for NIDS (Snort) pattern matching using a combination of te...
A circuit and an associated lightweight protocol have been developed to secure communication between a control console and remote programmable network devices1 . The circuit provi...
Haoyu Song, Jing Lu, John W. Lockwood, James Mosco...
Dynamically Reconfigurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixte...
General purpose computing architectures are being called on to work on a more diverse application mix every day. This has been fueled by the need for reduced time to market and ec...
This paper presents ADB, an Alternate Wire Database, suitable for routing, tracing, and browsing in Xilinx Virtex, Virtex-E, Virtex-II, and Virtex-II Pro FPGAs. While mainstream d...
Reconfigurable System-on-Chip (SoC) platforms that incorporate hard-core processors surrounded by large amounts of FPGA are today commodities: the reconfigurable logic is often us...
This paper describes the package of test bench code required to verify the Algotronix' AES IP Core. Several authors (see the references in [3]) have published papers detailing...
This poster proposes a technique, based on polynomial approximation, which can be applied to convert ROMs into a combination of arithmetic operations and smaller ROMs. We show tha...
Gareth W. Morris, George A. Constantinides, Peter ...