Sciweavers

FCCM
2004
IEEE
103views VLSI» more  FCCM 2004»
14 years 2 months ago
A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder
The development of turbo codes has allowed for nearShannon limit information transfer in modern communication systems. Although turbo decoding is viewed as superior to alternate d...
Jian Liang, Russell Tessier, Dennis Goeckel
FCCM
2004
IEEE
102views VLSI» more  FCCM 2004»
14 years 2 months ago
Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications
We demonstrate the use of a "smart camera" to accelerate two very different image processing applications. The smart camera consists of a high quality video camera and f...
Miriam Leeser, Shawn Miller, Haiqian Yu
FCCM
2004
IEEE
175views VLSI» more  FCCM 2004»
14 years 2 months ago
A Flexible Hardware Encoder for Low-Density Parity-Check Codes
We describe a flexible hardware encoder for regular and irregular low-density parity-check (LDPC) codes. Although LDPC codes achieve achieve better performance and lower decoding ...
Dong-U Lee, Wayne Luk, Connie Wang, Christopher Jo...
FCCM
2004
IEEE
101views VLSI» more  FCCM 2004»
14 years 2 months ago
Hardware-in-the-Loop Evolution of a 3-bit Multiplier
Gregory V. Larchev, Jason D. Lohn
FCCM
2004
IEEE
130views VLSI» more  FCCM 2004»
14 years 2 months ago
Hyperreconfigurable Architectures for Fast Run Time Reconfiguration
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit changing needs of a computation during run time. The increasing...
Sebastian Lange, Martin Middendorf
FCCM
2004
IEEE
136views VLSI» more  FCCM 2004»
14 years 2 months ago
The MOLEN Processor Prototype
We present a prototype design of the MOLEN polymorphic processor, a CCM based on the co-processor architectural paradigm. The Xilinx Virtex II Pro technology is used as a prototyp...
Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassi...
FCCM
2004
IEEE
112views VLSI» more  FCCM 2004»
14 years 2 months ago
ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...
FCCM
2004
IEEE
97views VLSI» more  FCCM 2004»
14 years 2 months ago
Unidirectional Switch-Boxes for Synthesizable Reconfigurable Arrays
Sami Khawam, Tughrul Arslan, Fred Westall
FCCM
2004
IEEE
121views VLSI» more  FCCM 2004»
14 years 2 months ago
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
Alireza Hodjat, Ingrid Verbauwhede
FCCM
2004
IEEE
91views VLSI» more  FCCM 2004»
14 years 2 months ago
An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding
We propose a parallel architecture for implementing the interpolation step in the Koetter-Vardy soft-decision ReedSolomon decoding algorithm. The key feature is the embedding of b...
Warren J. Gross, Frank R. Kschischang, P. Glenn Gu...