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    ARITH
    1999
    IEEE
    153views Applied Computing» more  ARITH 1999»
    Reduced Latency IEEE Floating-Point Standard Adder Architectures
    14 years 4 months ago
    Reduced Latency IEEE Floating-Point Standard Adder Architectures
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    The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
    Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
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