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    A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
    13 years 6 months ago
    A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
    Download  www.ece.ucdavis.edu
    A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
    Zhiyi Yu, Bevan M. Baas
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