Sciweavers

FMCAD
2008
Springer
13 years 9 months ago
Automatic Generation of Local Repairs for Boolean Programs
Automatic techniques for software verification focus on obtaining witnesses of program failure. Such counterexamples often fail to localize the precise cause of an error and usuall...
Roopsha Samanta, Jyotirmoy V. Deshmukh, E. Allen E...
FMCAD
2008
Springer
13 years 9 months ago
BackSpace: Formal Analysis for Post-Silicon Debug
Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall ...
Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steve...
FMCAD
2008
Springer
13 years 9 months ago
Verifying an Arbiter Circuit
Abstract--This paper presents the verification of an asynchronous arbiter modeled at the circuit level with non-linear ordinary differential equations. We use Brockett's annul...
Chao Yan, Mark R. Greenstreet
FMCAD
2008
Springer
13 years 9 months ago
Invariant-Strengthened Elimination of Dependent State Elements
Abstract-- This work presents a technology-independent synthesis optimization that is effective in reducing the total number of state elements of a design. It works by identifying ...
Michael L. Case, Alan Mishchenko, Robert K. Brayto...
FMCAD
2008
Springer
13 years 9 months ago
Scheduling Optimisations for SPIN to Minimise Buffer Requirements in Synchronous Data Flow
Synchronous Data flow (SDF) graphs have a simple and elegant semantics (essentially linear algebra) which makes SDF graphs eminently suitable as a vehicle for studying scheduling o...
Pieter H. Hartel, Theo C. Ruys, Marc C. W. Geilen
FMCAD
2008
Springer
13 years 9 months ago
Scaling Up the Formal Verification of Lustre Programs with SMT-Based Techniques
We present a general approach for verifying safety properties of Lustre programs automatically. Key aspects of the approach are the choice of an expressive first-order logic in wh...
George Hagen, Cesare Tinelli
FMCAD
2008
Springer
13 years 9 months ago
Recording Synthesis History for Sequential Verification
Performing synthesis and verification in isolation has two undesirable consequences: (1) verification runs the risk of becoming intractable, and (2) strong sequential optimization...
Alan Mishchenko, Robert K. Brayton
FMCAD
2008
Springer
13 years 9 months ago
A Theory of Mutations with Applications to Vacuity, Coverage, and Fault Tolerance
The quality of formal specifications and the circuits they are written for can be evaluated through checks such as vacuity and coverage. Both checks involve mutations to the specif...
Orna Kupferman, Wenchao Li, Sanjit A. Seshia