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FPGA
2010
ACM
359views FPGA» more  FPGA 2010»
14 years 9 months ago
Towards scalable placement for FPGAs
Placement based on simulated annealing is in dominant use in the FPGA community due to its superior quality of result (QoR). However, given the progression of FPGA device capacity...
Huimin Bian, Andrew C. Ling, Alexander Choong, Jia...
FPGA
2010
ACM
276views FPGA» more  FPGA 2010»
14 years 9 months ago
Accelerating Monte Carlo based SSTA using FPGA
Monte Carlo based SSTA serves as the golden standard against alternative SSTA algorithms, but it is seldom used in practice due to its high computation time. In this paper, we acc...
Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, K...
FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
14 years 9 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 9 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
14 years 9 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
FPGA
2010
ACM
173views FPGA» more  FPGA 2010»
14 years 9 months ago
Global delay optimization using structural choices
Alan Mishchenko, Robert K. Brayton, Stephen Jang